Appendix B: Page Table Entry Bitfields
x86-64 Page Table Entry (PTE)
Each page table entry is 64 bits (8 bytes). Not all bits are used — the CPU ignores some, and the OS can repurpose them.
63 62..52 51..12 11..9 8 7 6 5 4 3 2 1 0
+---+-------+----------------------+-----+---+---+---+---+---+---+---+---+---+
|NX | Avail | Physical Page Number | AVL | G |PAT| D | A |PCD|PWT|U/S|R/W| P |
+---+-------+----------------------+-----+---+---+---+---+---+---+---+---+---+
Bit-by-Bit Reference
+------+--------+-----------------------------------------------------------+
| Bit | Name | Meaning |
+------+--------+-----------------------------------------------------------+
| 0 | P | Present. 1 = page is in physical memory. |
| | | 0 = not present; access triggers page fault (#PF). |
+------+--------+-----------------------------------------------------------+
| 1 | R/W | Read/Write. 1 = writable. 0 = read-only. |
| | | Write to read-only page triggers page fault. |
+------+--------+-----------------------------------------------------------+
| 2 | U/S | User/Supervisor. 1 = user-mode (ring 3) can access. |
| | | 0 = kernel-only. User access triggers page fault. |
+------+--------+-----------------------------------------------------------+
| 3 | PWT | Page-level Write-Through. 1 = write-through caching. |
| | | 0 = write-back caching (normal). |
+------+--------+-----------------------------------------------------------+
| 4 | PCD | Page-level Cache Disable. 1 = caching disabled. |
| | | Used for memory-mapped I/O (device registers). |
+------+--------+-----------------------------------------------------------+
| 5 | A | Accessed. Set by CPU when page is read or written. |
| | | OS clears it periodically to track working set. |
+------+--------+-----------------------------------------------------------+
| 6 | D | Dirty. Set by CPU when page is written to. |
| | | OS uses this to know which pages need writing to disk. |
+------+--------+-----------------------------------------------------------+
| 7 | PS/PAT | Page Size (in PDE): 1 = large page (2MB or 1GB). |
| | | PAT (in PTE): Page Attribute Table index bit. |
+------+--------+-----------------------------------------------------------+
| 8 | G | Global. 1 = don't flush from TLB on CR3 switch. |
| | | Used for kernel pages shared across all processes. |
+------+--------+-----------------------------------------------------------+
| 9-11 | AVL | Available for OS use. Linux uses these for swap info, |
| | | soft-dirty tracking, and other bookkeeping. |
+------+--------+-----------------------------------------------------------+
|12-51 | PPN | Physical Page Number. The upper bits of the physical |
| | | address (shift left by 12 to get byte address). |
+------+--------+-----------------------------------------------------------+
|52-62 | Avail | Available / reserved. Some used by OS or hardware. |
+------+--------+-----------------------------------------------------------+
| 63 | NX | No-Execute. 1 = code execution forbidden on this page. |
| | | Attempting to execute triggers page fault. |
| | | Critical for W^X security (stack, heap are NX). |
+------+--------+-----------------------------------------------------------+
How the OS Uses These Bits
Scenario Bits set
----------------------------------------------
Normal code page: P=1, R/W=0, U/S=1, NX=0
Writable data page: P=1, R/W=1, U/S=1, NX=1
Stack page: P=1, R/W=1, U/S=1, NX=1
Kernel code: P=1, R/W=0, U/S=0, NX=0
Copy-on-Write page: P=1, R/W=0 (trap on write)
Demand-paged (not loaded): P=0 (trap on any access)
Guard page (stack boundary): P=0 (trap = stack overflow)
ARM Comparison
ARM uses a different page table format, but the concepts are the same:
x86-64 Bit ARM Equivalent Notes
----------- ---------------- --------------------------------
P (Present) Valid bit Same concept
R/W AP[2:1] Access Permission bits
U/S AP[1], PXN, UXN More granular in ARM
NX XN / UXN / PXN Separate execute control for
user and privileged modes
D (Dirty) DBM (Dirty Bit Hardware-managed on newer ARM
Management)
A (Accessed) AF (Access Flag) Same concept
ARM page tables can be 4KB, 16KB, or 64KB granules (x86-64 is always 4KB base). ARM also supports 3-level or 4-level page tables depending on the virtual address size configuration.